| abstract |
The present invention relates to a memory device using a multi-walled nanotube cell, and discloses a technique capable of reducing the overall memory size by efficiently arranging a cross-point cell array including a capacitor element and a PNPN nanotube switch. According to the present invention, a multi-walled nanotube cell array 40 composed of a PNPN nanotube switch and a capacitor element that does not require a separate gate control signal is connected to a word line driving unit 50, a sense amplifier 60, a data bus 70, a main amplifier 80, By disposing the cell array region and the circuit element region on the basis of the interlayer insulating film, the entire chip size can be reduced by disposing the data buffer 90 and the circuit element region 150 including the input / output port 100 and the like. Like that. [Selection] Figure 11 |