| abstract |
PROBLEM TO BE SOLVED: To reduce the cell area of a non-volatile memory composed of a single-layer polysilicon gate and operate with ultra-low power consumption. [Solution] A reverse bias such as -5 V is applied to the P-type impurity region 11 provided on the substrate surface of the N-type well 4 at the lower end of the floating gate 6 with the gate oxide film 5 interposed therebetween and the junction formed by the N-type well 4. Writing is performed by applying a voltage and injecting hot electrons generated by the band-to-band tunnel phenomenon into the floating gate 6. Since the programming time is approximately 10 μs and the leakage current of the junction during the programming operation can be designed to be about 100 nA, the energy required for programming is reduced to 5 pJ, and programming using channel hot electron injection of the conventional stacked gate type memory cell is performed. The energy can be reduced to 1/100 or less. [Selection] Figure 1 |