http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005165508-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-28 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-362 |
| filingDate | 2003-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bf8f485d14eff89ccd452bfb4b24885 |
| publicationDate | 2005-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2005165508-A |
| titleOfInvention | Direct memory access controller |
| abstract | PROBLEM TO BE SOLVED: To provide a DMAC which prevents a specific DMA channel from monopolizing a bus right. A DMAC1 includes a plurality of DMA transfer units 20-1 to 20-n that control DMA transfer according to values set in register groups 21 to 26 for current transfer. When the DMAC acquires the bus right from the bus master, the use of the bus is permitted to a plurality of DMA transfer units in a predetermined order in response to transfer requests from the plurality of DMA transfer units 20-1 to 20-n. Therefore, it is possible to prevent a specific DMA channel from monopolizing the bus right. [Selection] Figure 3 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8606974-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008046771-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009110335-A |
| priorityDate | 2003-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.