http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005150309-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d5c039f60302b61e712887aa2267ecbe |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-13055 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-1305 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-36 |
| filingDate | 2003-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c7078da7b35c20955f6d692786299511 |
| publicationDate | 2005-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2005150309-A |
| titleOfInvention | Semiconductor device |
| abstract | An object of the present invention is to reduce the temperature cycle stress received by a solder 7 even when an inexpensive material such as copper or aluminum is used for the metal base plate 1 with an easy configuration without requiring protrusions. Provided is a semiconductor device. A ceramic substrate, a first surface side wiring pattern formed on a first surface of the ceramic substrate, a second surface side wiring pattern formed on a second surface of the ceramic substrate, and the ceramic substrate. A plurality of semiconductor circuit parts having one or two semiconductor elements 3 mounted on the first surface side wiring pattern 4 side of the second surface side wiring pattern 5 of the ceramic substrate 2 of each semiconductor circuit part. The joining member 7 which is applied to the entire area of the second surface of the ceramic substrate 2 including the range immediately below the semiconductor element 3 on the side, and a metal member having a linear expansion coefficient larger than that of the ceramic substrate 2 And a metal base plate 1 to which a plurality of semiconductor circuit portions are joined via a metal plate. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9018756-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007158156-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104241208-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011233722-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8659900-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011155227-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4549287-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008244118-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2015002305-A |
| priorityDate | 2003-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.