http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005150299-A

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filingDate 2003-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2005-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2005150299-A
titleOfInvention SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, CIRCUIT BOARD, AND ELECTRONIC DEVICE
abstract PROBLEM TO BE SOLVED: To provide a semiconductor chip capable of satisfactorily stacking a three-dimensional chip by suppressing bonding failure caused by warping of the chip or the like in a three-dimensional chip stacking technique or suppressing the outflow of solder. A semiconductor chip (41) includes a substrate (10) and a post electrode (45) protruding from a surface (10S) of the substrate (10), and a protrusion (2) protruding from the post electrode (45) is provided on a surface (10S) near the post electrode (45). [Selection] Figure 1
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102299136-A
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011135084-A
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019160984-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9831164-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2016132830-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7109619-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106505060-A
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Total number of triples: 27.