http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005093072-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 |
| filingDate | 2004-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2f0b986f5b584a6000d6226848ae1f5d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8250c7310059b3216b9e34c1cfc0a526 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca5e5aede7f632184d261f650d4cc272 |
| publicationDate | 2005-04-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2005093072-A |
| titleOfInvention | Synchronous semiconductor memory device |
| abstract | PROBLEM TO BE SOLVED: To improve response characteristics to a control signal of a synchronous semiconductor memory device without increasing current consumption. Means (2180, 3560) for generating first and second internal clock signals (SK, ZSKD) out of phase with each other in response to an external clock signal (K), and first and second Means (3550, 3554, 3556) for sampling the device activation signal (CS) when the logic levels of the internal clock signals are the same, and a predetermined time width in response to the signal sampled by the sampling means. Means (3558, 3562, 3564, 3566, 3568, 3570, 3572, 3574) for generating a pulse signal (SLC) having a control signal (extφ) in response to the pulse signal. Means (3570) for generating a control signal. [Selection] FIG. 64 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111045955-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111045955-A |
| priorityDate | 1993-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.