http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005038964-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d78fe473c8a29219129bbc8bb50f6a59
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20
filingDate 2003-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8cd812480f3d63636b047bea9869968c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_adbc648b22c21e73fa9811ef52b83133
publicationDate 2005-02-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2005038964-A
titleOfInvention Semiconductor wafer and manufacturing method thereof
abstract A low-cost semiconductor wafer having a strained Si layer with low dislocation defect density and good crystallinity, and a method for manufacturing the same. A semiconductor wafer comprising at least a silicon single crystal substrate, a SiGe layer epitaxially grown on the silicon single crystal substrate, and an Si layer epitaxially grown on the SiGe layer, the silicon single crystal A semiconductor wafer characterized in that the surface layer of the substrate and / or the SiGe layer is made porous, and at least the surface layer of the silicon single crystal substrate is made porous to form a porous Si layer, A heat treatment for smoothing the surface of the formed porous Si layer is performed, a SiGe layer is epitaxially grown on the surface of the smoothed porous Si layer after the heat treatment, and a Si layer is epitaxially grown on the surface of the grown SiGe layer A method for manufacturing a semiconductor wafer. [Selection] Figure 1
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priorityDate 2003-07-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 25.