| abstract |
A method of manufacturing a semiconductor device having an alignment mark, the method comprising forming a first dielectric layer, etching a groove having a predetermined dimension in the first dielectric layer, and removing a first layer of metal from the groove. Depositing a second dielectric layer on the first dielectric layer and the first layer of metal; and simultaneously etching lines and openings in the second dielectric layer, comprising: One line is used as a via that extends to the first layer of metal and a step of filling the line and the opening, wherein the filling is controlled to fill the line and underfill the opening. Performing a chemical mechanical polishing of the plating and depositing an opaque stack of layers on the metal, wherein the opaque stack of layers is flush with the surface of the underfilled opening. So that the alignment mark is continuous And in order to align the layers, and a step in the opaque stack of layers. |