| abstract |
A high speed erase of a MONOS memory cell is provided. A first gate insulating layer made of an insulating film of a compound containing at least silicon and oxygen, and a first gate insulating layer in contact with the first gate insulating layer and made of a silicon nitride film, a silicon oxynitride film or an alumina film. Charge storage layer 5, second charge storage layer 62 thicker than first gate insulation layer 4, second charge storage layer 62 in contact with second insulation layer 61, and second charge storage layer 62 in contact with second charge storage layer 62. A gate insulating layer including a third insulating layer 63 thicker than the first gate insulating layer 4, and a control electrode 7 formed on the third insulating layer 63. The first gate insulating layer 4 may include a silicon oxynitride film having a higher oxygen composition than the first charge storage layer 5. The second insulating layer and the third insulating layer may have a thickness greater than 3 nm. A structure in which an acceptor impurity is added to the second charge storage layer 62 may be used. [Selection diagram] Fig. 1 |