| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B60Y2304-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-2024
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B60R2011-0066 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B62D1-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0804
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B60R21-2037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0893
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0864 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-15
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-41 |
| filingDate |
2003-05-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd5f3895a2a03d1714768030eeaec2d6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01a9dc16df223f6dfb60efed8c859658
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1d16170fe48316f2ecb378640106b46b |
| publicationDate |
2004-11-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2004334996-A |
| titleOfInvention |
Semiconductor device |
| abstract |
When a storage capacity of a memory is increased by using a conventional SRAM, a chip size increases and a cost increases. Further, there is a problem that the data holding current increases. An SESO memory or a phase change memory having a smaller memory cell area than an SRAM is used. It has a plurality of memory banks including SESO and phase change memory. A cache memory having a ratio of the writing speed (m) to the reading speed (n) and the number of ways of (m / n) is used. The write-back operation from the cache is controlled so as not to be continued in the same memory bank. By using a highly integrated memory cell, a memory having a large data storage capacity can be realized without increasing the chip size. A memory with a small data holding current can be realized. By using a small amount of cache memory, a data processing system in which external access is not delayed even when a memory with a low writing speed is used can be realized. [Selection diagram] Fig. 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011258193-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9384134-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006190402-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8717810-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8694737-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9448938-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8613074-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9075725-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8111559-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012150875-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006295130-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9317450-B2 |
| priorityDate |
2003-05-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |