| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_73ebc284a55d5daf0e209d6186c9e65c |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate |
2002-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_664b01c7e4f387bd43c1643b1d29f246 |
| publicationDate |
2004-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2004111629-A |
| titleOfInvention |
Method for manufacturing semiconductor device |
| abstract |
An object of the present invention is to provide a method of manufacturing a semiconductor device including a nonvolatile memory device having resistance to deterioration during data writing / erasing. A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device including a memory region forming a memory cell array in which nonvolatile memory devices are arranged in a matrix, wherein a first memory device is provided above a semiconductor substrate. A gate insulating layer 12 is formed, a first conductive layer word gate 14 and a stopper layer are formed, and a first insulating layer 22 and a second conductive layer are formed on the entire surface of the memory region. A first sidewall conductive layer is formed by anisotropic etching, a third conductive layer is formed on the entire surface of the memory region, and a second sidewall conductive layer 242 is formed by anisotropic etching; The control gates 20 and 30 are formed by isotropically etching the first and second sidewall conductive layers. [Selection] Fig. 2 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7939448-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7791129-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7816207-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013077841-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7709874-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2007086304-A1 |
| priorityDate |
2002-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |