http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2004006987-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_73ebc284a55d5daf0e209d6186c9e65c |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 |
| filingDate | 2003-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c6369e6f4febe7fdb9ca9c75af8bcbb3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_146532f1791b633fdcbe65ec4435f4e0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3ad8ef1263e217064014f58c2ce16f0a |
| publicationDate | 2004-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2004006987-A |
| titleOfInvention | Integrated circuit device |
| abstract | PROBLEM TO BE SOLVED: To provide an integrated circuit device capable of incorporating upper layers of various configurations while maintaining high performance of a circuit of a physical layer, and an electronic device using the same. SOLUTION: A macro cell MC1 including a USB 2.0 physical layer circuit is arranged at a corner of an integrated circuit device ICD. The data terminals DP and DM are arranged in the I / O area IOR1 along the side SD1, and the power supply terminals PVDD, PVSS, XVDD, and the like of the clock generation circuit 14 and the sampling clock circuit 22 are arranged in the I / O area IOR2 along the side SD2. XVSS and clock terminals XI and XO are arranged. An interface area with the macro cell MC2 including the user logic is provided along the side SD3. The reception circuit 100 is arranged on the DR1 side of the IOR1, the clock generation circuit 14 is arranged on the DR2 side of the IOR2, and the sampling clock generation circuit 22 is arranged on the DR1 side of the reception circuit 100 and the DR2 side of the clock generation circuit 14. The transmitting circuit 104 is arranged on the DR2 side of the receiving circuit 100 and on the DR1 side of the data terminals DP and DM. [Selection] Fig. 9 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014504844-A |
| priorityDate | 2003-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 53.