http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2003309194-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd83260a96356882b5f50dd097411a72 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S257-90 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S257-909 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0475 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate | 2002-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca8044ab092e5b1c340617369807350f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3eedc00baf3a3e9a1c665786a27e193a |
| publicationDate | 2003-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2003309194-A |
| titleOfInvention | Semiconductor memory device and manufacturing method thereof |
| abstract | (57) [Summary] (With correction) [PROBLEMS] To provide a semiconductor memory device which stores a plurality of bits per cell, and which can be made higher in density with a simple configuration. A plurality of first gate electrodes extending in parallel with each other in one direction, and a plurality of second gate electrodes extending in a direction intersecting with the plurality of first gate electrodes are provided. A diffusion layer is provided on a substrate surface of a plurality of sections divided in a matrix by the first gate electrode and the second gate electrode, and one of the sections is independently formed. Having an accessible 4-bit storage node, A diffusion layer in a section is connected by a contact (CT), extends along one diagonal direction of the section, and diffuses in a plurality of sections in a matrix in another section which is on an extension of the diagonal line. A wiring 112 is provided which is connected to each of the layers by a contact, and a plurality of the wirings are arranged to extend obliquely in the memory cell array region in parallel with each other. |
| priorityDate | 2002-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.