| abstract |
(57) Abstract: A semiconductor integrated circuit device capable of reading stored information from an on-chip nonvolatile memory cell transistor at high speed is provided. A memory cell transistor has a first well region, a pair of memory electrodes, one of which is a source electrode and the other is a drain electrode, and a channel region sandwiched between the pair of memory electrodes. On the channel region, a first gate electrode (3) disposed near the memory electrode via an insulating film (2), and a first gate electrode (3) disposed via an insulating film (4, 7) and a charge storage region (6). A second gate electrode electrically separated from the first gate electrode; The first A first negative voltage is applied to the well region to form a reverse bias state higher than the junction withstand voltage between the memory electrode and the memory electrode near the second gate electrode so that hot electrons can be injected into the charge storage region. The region can be injected into the charge storage region. |