http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2003273329-A

Outgoing Links

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filingDate 2002-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9bf578145227d414667f168f79fb7ce5
publicationDate 2003-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2003273329-A
titleOfInvention Semiconductor storage device
abstract (57) Abstract: A ferroelectric memory capable of reducing a memory cell block size, further reducing bit line capacity, and increasing read signals. A memory cell includes a ferroelectric capacitor having one end and the other end connected between a source and a drain of a cell transistor. A memory cell block MCB0 includes a plurality of memory cells connected in series. A block select transistor BT0 for selecting the cell block MCB0, a metal wiring BR0 connected between one end of the cell block MCB0 and one end of the current path of the select transistor BT0, and the other end of the current path of the select transistor BT0. The connected bit line / BL and bit line / B And a select transistor BT1, B connected to one end of a current path to the bit line BL. T1 ′, and the gate wiring of the selection transistors BT1, BT1 ′ is arranged below the metal wiring BR0.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006332335-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2010033624-A
priorityDate 2002-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 20.