Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F5-06 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F5-06 |
filingDate |
2001-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e9264f2cd315f122c409c59ccb4f8549 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cc131293628479a075a6711047ed2250 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_67064c0cb4220aa75b71ceca06068cae |
publicationDate |
2003-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
JP-2003157228-A |
titleOfInvention |
Data transfer circuit |
abstract |
(57) Abstract: An object of the present invention is to reduce a delay in data transfer when data is transferred between regions having different operating frequencies. A data transfer circuit includes a first buffer operating in a first clock cycle, a plurality of second buffers operating in a second clock cycle, and receiving data in the first clock cycle. Buffer or second , And a selector circuit for selectively supplying data to the buffer. |
priorityDate |
2001-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |