http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2003078010-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 |
| filingDate | 2001-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_83139433b7815d9646ec70f7cb110ede |
| publicationDate | 2003-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2003078010-A |
| titleOfInvention | Semiconductor integrated circuit device |
| abstract | Abstract: PROBLEM TO BE SOLVED: To improve the degree of freedom of wiring layout on a fuse forming region of a semiconductor integrated circuit device and reduce the area occupied by fuses and wiring. SOLUTION: A fuse F is formed by wiring in the same layer as or above the signal wiring S, and an opening OA is formed in a guard ring G which is formed so as to surround the fuse F and is a wall made of a conductive film laminated film. To pass through the signal wiring S. As a result, the degree of freedom of the layout of the signal wiring S increases. Also, The area occupied by the fuse F and the signal wiring S can be reduced. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8435840-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-100364096-C http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7888770-B2 |
| priorityDate | 2001-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.