| abstract |
(57) [Summary] To reduce the memory cell size of an SRAM. An SRAM memory cell includes a transfer MIS. FET, MISFET for driving and MISFET for load And the load MISFET is a drive MI It is formed above the SFET. MISFET for load A gate electrode 2 on a side surface of the stacked structure P extending in a direction perpendicular to the main surface of the semiconductor substrate 1 via a gate insulating film 22; 3 has a vertical structure. This laminated structure P Is composed of a polycrystalline silicon film, and the lower semiconductor layer 13, the intermediate semiconductor layer 14, and the upper semiconductor layer 15 Are laminated. |