http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2003016130-A

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filingDate 2001-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_85caaaf70b39381e29bf541f31e4ce50
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publicationDate 2003-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2003016130-A
titleOfInvention Clock distribution method, clock tree generation method, clock delay setting method, and wiring processing method
abstract (57) [Summary] [PROBLEMS] To maximize the circuit yield and maximize the clock frequency by allocating an optimal clock skew using useful skew. SOLUTION: A margin of F / Fi is obtained in consideration of conditions of flip-flops before and after F / Fi constituting a logic circuit, and the Di of F / Fi is positioned almost at the center of the margin. By adjusting the clock skew, even if the operation timing of the F / Fi is shifted due to a variation in the manufacturing process, the shift can be absorbed by the margin, and a logic circuit that operates normally as a circuit can be manufactured. Therefore, the yield of the circuit can be maximized. Also, the clock frequency can be maximized by increasing the clock frequency until the margin disappears.
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