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filingDate 2000-02-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2002-10-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2002536846-A
titleOfInvention Method of manufacturing vertical metal connections in integrated circuits
abstract An integrated circuit having a copper metallization level is provided using a damascene type process for making integrated circuit vias to prevent copper particles from diffusing into a dielectric material. SOLUTION: At least one layer of a dielectric material 3 is deposited on a copper track 1 covered by an encapsulation layer 2. The cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited on the cavity to eliminate copper 7 diffusion. The protective layer 7 at the bottom of the cavity 6 is anisotropically etched, and the encapsulation layer 2 is also etched, after which the cavity is filled with copper. During the etching of the encapsulation layer, the finely divided copper particles do not contaminate the dielectric material 3.
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