| abstract |
SUMMARY OF THE INVENTION The present invention generally relates to silane-based processes with certain process parameters on electronic devices such as semiconductors useful for forming suitable barrier, etch stop and passivation layers for integrated circuit applications. An improved process for depositing silicon carbide using a reduced material is provided. In the preferred embodiment, a specific silicon carbide material is used as the barrier layer to reduce copper diffusion and also to minimize the contribution of the barrier layer to capacitive coupling between connection lines. Can also. It can be used, for example, as an etch stop under an intermetal dielectric (IMD), especially if the IMD is a low k value silane based IMD. In another embodiment, it may be used to form a passivation layer that is resistant to moisture and other adverse conditions. Each of these aspects is applicable to dual damascene structures. |