| abstract |
(57) [Summary]nIn the 256 Meg dynamic random access memory, a plurality of cells constitute an independent array, and the plurality of independent arrays are constructed in a 32 Meg array block, and the array block is constructed in a 64 Meg quadrant. The sense amplifiers are located between adjacent rows of the independent array, and the row decoders are located between adjacent columns of the independent array. In some gap cells, a multiplexer is provided for transmitting a signal from an I / O line to a data line. Further, a data path including an array I / O block is provided, and the data path extends from each of the quadrants for outputting data to data lines from a data read multiplexer, a data buffer, and a data driver pad. Responsive. The write data path includes data in the buffer and in a data write multiplexer for providing data to the array I / O blocks. A power bus is provided to minimize external supply voltage routing, completely ring each array block, and distribute grid power within each array block. A plurality of voltage sources supply necessary voltages to the array and peripheral circuits. The power supply is configured to output power in response to a power request, and is configured to maintain a ratio between the power generation capability and the decoupling capacity at a desired value. A power-up sequence circuit is provided to control power-up of the chip. Redundant rows and columns are provided, as are the circuits required to logically replace defective rows and columns with operable rows and columns. Circuits that support various test mode configurations are provided as chips. |