http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002334579-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-409 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 |
| filingDate | 2002-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ff7d5e7780e0e6d1084d2472ad2ba49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f5a6469f6ca03a2c5d6f7cade1483542 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ef5b596f7d86f4459d08903b3b1ed5cc |
| publicationDate | 2002-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2002334579-A |
| titleOfInvention | Method and apparatus for reducing write operation time in dynamic random access memory |
| abstract | PROBLEM TO BE SOLVED: To provide a method for improving write time for a dynamic random access memory (DRAM) having a destructive read architecture. A method for preparing a dynamic random access memory (DRAM) cell for a write operation having a preset state is disclosed. In one exemplary embodiment, the method includes creating a preset voltage level in the cell prior to a delayed write back in the destructive read architecture, wherein the preset voltage level is a logic zero voltage level. And a logic 1 voltage level. A logic 0 voltage level corresponds to the first cell voltage value when the cell stores 0 bits therein, and a logic 1 voltage level corresponds to the second cell voltage value when the cell stores 1 bit therein. I do. Prior to creating a preset voltage level in the cell, the cell has an initial voltage value corresponding to either a logic zero voltage level or a logic one voltage level. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6937535-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-RE42976-E |
| priorityDate | 2001-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419505666 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID51712 |
Total number of triples: 21.