http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002303652-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_be055db3c1a09879df07379ba969e223
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R1-0735
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filingDate 2001-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_baa029fb764da27371e7bd2e40f614d0
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publicationDate 2002-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2002303652-A
titleOfInvention Inspection apparatus and inspection method for semiconductor integrated circuit
abstract (57) Abstract: When a sealed space formed by a wafer tray, a wiring substrate, and an annular sealing member is decompressed, a situation in which a peripheral portion of the wiring substrate is deformed toward the wafer tray is prevented, and bumps are formed. The durability is improved and the contact resistance between the bump and the external electrode is made uniform. SOLUTION: A hemispherical bump 104 is provided on a portion of an elastic sheet 103 fixed to a wiring board 101, the portion corresponding to an external electrode 2 of a semiconductor wafer 1. A plurality of dummy bumps 106 protruding toward the semiconductor wafer 1 are provided on a peripheral portion of the surface of the elastic sheet 103 facing the semiconductor wafer 1, and the plurality of dummy bumps 106 are provided on the wafer tray 111 and the annular seal. When the sealed space 118 formed by the member 112 and the wiring board 101 is decompressed, the wiring board 10 1 is prevented from deforming toward the wafer tray 111.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8689160-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2011125191-A1
priorityDate 2001-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Incoming Links

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Total number of triples: 33.