http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002271026-A
Outgoing Links
Predicate | Object |
---|---|
assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-40 |
filingDate | 2001-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6035999b15a160c2dbcec0708a73298 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_78a7dfb4e3ea756f9c496ea0145d4609 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a39944d8889f1bff02f0b3b6e560e43 |
publicationDate | 2002-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | JP-2002271026-A |
titleOfInvention | Multilayer printed wiring board and method of manufacturing multilayer printed wiring board |
abstract | (57) Abstract: A wiring pattern on a connection hole is formed flat, the connection hole is formed finer, and the wiring pattern is further thinned. A first wiring pattern is formed on a substrate, a thin film insulating layer is formed on the substrate provided with the first wiring pattern, and a first wiring pattern is formed on the thin film insulating layer. A connection hole 8 is formed so that the metal bump 3 faces the outside, a metal conductive layer 13 is formed on the thin film insulating layer 7 in which the connection hole 8 is formed, and the metal conductive layer 13 is selectively removed to form a metal bump. 9, an interlayer insulating layer 11 is formed on the thin film insulating layer 7, and a second wiring pattern 12 is formed on the interlayer insulating layer 11. |
isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2011049476-A |
priorityDate | 2001-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.