http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002269990-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
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filingDate 2001-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93c540d308876da2d06524ec1a32d54f
publicationDate 2002-09-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2002269990-A
titleOfInvention Nonvolatile semiconductor memory device and method of operating the same
abstract (57) Abstract: The operation efficiency is improved by optimizing the number of bits to be operated collectively in one row of one memory cell row of a VG type memory cell array. A memory cell array includes a plurality of memory cell arrays (a sub-array (not shown) constituting a memory cell array 1), and each of the memory cells arranged in a matrix in the sub-array includes: A memory transistor having charge storage means and a channel forming region and cascaded between memory cells in the same row; A control gate capacitively coupled to a channel formation region of the memory transistor. The control gate lines connected to the control gates are driven, and each of the sub-arrays is electrically connected to a number suitable for operating the plurality of sub-arrays in parallel in accordance with the data input or output speed of the nonvolatile semiconductor memory device. And a control circuit 5 that divides the control circuit into two.
priorityDate 2001-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 17.