http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002231936-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8f063b8222ec3c8e746a415e7f364473
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-43
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
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filingDate 2001-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_872483ef8c3e562574a75a5c65f8c517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4f416861ffdf0db4a6630c990d9eaf6f
publicationDate 2002-08-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2002231936-A
titleOfInvention Method for preventing bump formation on side wall of metal silicide layer of gate electrode and method for manufacturing gate electrode
abstract (57) Abstract: Provided are a method for preventing a bump from being formed on a side wall of a metal silicide layer of a gate electrode, and a method for manufacturing a gate electrode. The method comprises: (a) providing a gate electrode structure formed on a semiconductor substrate; and (b) using a mixed gas containing nitrogen gas and hydrogen gas for the gate electrode structure. Applying annealing (RTA); (C) subjecting the gate electrode structure to thermal oxidation for a short time. The present invention also provides (a) providing a chamber and a gate electrode structure formed on a semiconductor substrate; and (b) placing the gate electrode structure in the chamber and clearing oxygen gas in the chamber. To do, (C) Short-time annealing (RTA) for the gate electrode structure And (d) subjecting the gate electrode structure to thermal oxidation for a short time.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007173762-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006005323-A
priorityDate 2001-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 28.