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filingDate 2001-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ee786dd093a96eff4eb6db98eb424e57
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publicationDate 2002-07-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2002208701-A
titleOfInvention MIS semiconductor device
abstract (57) [Summary] (with correction) [PROBLEMS] To improve a trade-off relationship between on-voltage and turn-off loss of a MIS semiconductor device such as an IGBT. An n + contact region and ap + contact region are formed in a first epitaxial layer deposited on a low resistance n + semiconductor substrate. N for the second epitaxial layer A + emitter region 14, a p base region 16, and an n − channel region 15 are formed. Emitter region 14, base region 1 A polysilicon gate electrode 18 is formed on the gate electrode 6 via a gate insulating film, and is covered with insulating films 19 and 20. Lateral direction (EL O) An n − drift layer 21 is formed from the surface of the channel region 15 by epitaxial growth. n - drift layer 2 An n + buffer layer 22 and ap + collector layer 23 are formed on the surface of the substrate 1. Thereby, the strength of the thin-film collector IGBT is increased and the processing is facilitated. Further, the step of bonding the bidirectional IGBT is avoided, and the processing is facilitated while maintaining the mechanical strength.
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