| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_294881271413951a95f284b588a68e66 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S257-908
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7923
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 |
| filingDate |
2001-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fac171fc48c782d53657df0201f129d6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0658024b5d0ca8f09b8be715b93b48c1 |
| publicationDate |
2002-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2002203918-A |
| titleOfInvention |
Nonvolatile semiconductor memory device and method of manufacturing the same |
| abstract |
(57) [Problem] To prevent the generation of a conductive residue that short-circuits between word lines. A memory cell includes a channel forming region CH; Charge storage film CSF comprising a plurality of stacked dielectric films And two storage units each including a region of the charge storage film CSF overlapping on both ends of the channel formation region CH, and a single-layer dielectric film DF2 in contact with the channel formation region CH between the storage units. An auxiliary layer (for example, bit lines BL1 and BL2) formed on each of the two impurity regions S / D, and two first control units formed on the auxiliary unit with a dielectric film interposed therebetween and located on the storage unit. The electrodes CG1 and CG2 and the first space It has a second control electrode WL embedded insulated from the control electrodes CG1 and CG2 and in contact with the single-layer dielectric film DF2. Since the main area of the opposing surface of the first control electrodes CG1 and CG2 has a forward taper, the second control electrode WL No conductive residue is left during processing. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2004312009-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6809385-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7061043-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7307879-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007142358-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4629982-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005228957-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4608232-B2 |
| priorityDate |
2000-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |