| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3183
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 |
| filingDate |
2000-11-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0731649ea64ee85ec073cfe320d2f27a |
| publicationDate |
2002-06-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2002162444-A |
| titleOfInvention |
Test apparatus and test method for semiconductor integrated circuit |
| abstract |
(57) [Summary] [PROBLEMS] To appropriately test a memory section in a practical use state of a semiconductor integrated circuit. SOLUTION: A memory unit 1 operates by receiving an operation signal and operates to output a data signal from a data output unit 5 to the memory unit 1. And a logic unit 2 for receiving a data signal from the memory unit 1 in the data input unit 4 and testing the memory unit 1 in the semiconductor integrated circuit. A signal is applied, and an operation signal is supplied to the logic unit 2 to operate the logic unit 2. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2021072695-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7373566-B2 |
| priorityDate |
2000-11-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |