http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002140289-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-28 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-28 |
| filingDate | 2001-09-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fc7d41031e4ba6cbf7f8f3b5f5d3f15b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9dfd4ae8d2615229c46ed060757e7638 |
| publicationDate | 2002-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2002140289-A |
| titleOfInvention | Microcontroller DMA operation with adjustable word size transfer and address alignment / increment |
| abstract | (57) [PROBLEMS] A microcontroller direct memory access that enables a single read of a source address with a larger word size, and enables writing of multiple subword sizes to a target address (57) DM A) Provide a unit. A DMA unit includes hardware support for a single read of a source address in a source word size, but writes to a target address in an independent target word size. These are the source word size (321), the source increment size (323), and the target word size (32 2) and the target increment size (324) is enabled by an independent control register store. A byte shifter / register (305) that shifts the entire byte at a time to the next lower byte position allows the transfer of a large word to a destination having a small word size. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-100357925-C |
| priorityDate | 2000-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.