| abstract |
(57) [Summary] [PROBLEMS] To reduce power consumption by suppressing leakage current during standby while minimizing increase in circuit area, Further, the present invention provides a semiconductor integrated circuit capable of judging good or bad by an Iddq test. A logic circuit including a low threshold voltage transistor and a switching circuit including a standard threshold voltage transistor are provided. During operation, the switching circuit is turned on to supply a drive current to the logic circuit. Then, during standby, the switching circuit is turned off, the path of the leak current is cut off, and the generation of the leak current is suppressed. During the I ddq test, the IC tester applies different bulk bias voltages to the channel regions of the pMOS transistor and the nMOS transistor via the pads P1 and P2, respectively, so that the leakage current can be suppressed to a low level. Quality of the semiconductor integrated circuit can be determined. |