http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002100989-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_824bb1aae75ca5d96020013d2008f262 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/A23C9-156 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/A23L27-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/A23L27-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C11B9-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-38 |
| filingDate | 2000-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0fdbf257ca5647538cbb2397525ea0e9 |
| publicationDate | 2002-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2002100989-A |
| titleOfInvention | Analog / digital converter |
| abstract | (57) [Problem] To improve the conversion throughput by making it possible to vary conversion accuracy and conversion time for each channel of an analog input signal of a plurality of channels of an ADC. An analog-to-digital conversion circuit for successively comparing analog input signals of a channel selected by a channel selector. When the AD conversion of all bits is completed, the first conversion completion flag is output when the AD conversion of all bits is completed in the ADC that performs the AD conversion and the operation of sequentially determining from MSB to LSB in order from MSB to LSB. Until the AD conversion with the first bit precision is completed, the first in-conversion indication flag is output, and the first A second interrupt request signal is selectively output when the A / D conversion with the bit precision of the second is completed, and the second conversion indicating that the A / D conversion with the second bit precision is completed in the middle of the A / D conversion AD conversion control circuit that outputs an end flag 30 and a register 21 for holding an AD conversion result. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7224371-B2 |
| priorityDate | 2000-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.