http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002093917-A

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filingDate 2001-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fbbb7fdb8849d1fdcbd3161bbe82fa64
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publicationDate 2002-03-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2002093917-A
titleOfInvention Testing methods for integrated circuits
abstract (57) Abstract: The present invention provides a test method for an integrated circuit. A process for evaluating the occurrence or possibility of a failure in an integrated circuit. The process involves forming a conductive region, such as a runner, around the substrate or die. The conductive regions are located on one or more different metallization layers in the integrated circuit. The conductive region is coupled to one or more bonding pads. Dice are resistance, Conductivity, crosstalk or other electrical properties on the conductive area are evaluated by measuring through the bonding pad. The evaluation can be used to predict if a runner formed in the integrated circuit has failed or is likely to fail.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016090578-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9658279-B2
priorityDate 2000-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 25.