http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002073364-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8a25bfd91c883be967b15c27983cb95e |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-02 |
| filingDate | 2000-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_518f55bd4488d399d8c1db09a137a0d1 |
| publicationDate | 2002-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2002073364-A |
| titleOfInvention | ASIC design method that facilitates soldering inspection |
| abstract | (57) [Abstract] [Problem] ASI that can easily check soldering failure It is intended to provide a design method of C. An ASIC includes a normal circuit, a selector circuit for selecting an output signal of the normal circuit and an output signal of a CPU interface circuit, and a tristate capable of controlling the output of the selector circuit to high impedance. It comprises buffers 6a, 6b, 6c, a CPU interface circuit 4 for controlling the selector circuit 5 and the tri-state buffers 6a, 6b, 6c, and a bus 7 for transmitting and receiving addresses and data to and from the CPU interface circuit 4. On the other hand, the ASIC 2 includes a normal circuit 8 and a CPU interface circuit 9 for monitoring an input level of an external input circuit. And a bus 10 for transmitting and receiving addresses and data to and from the CPU interface circuit 9. |
| priorityDate | 2000-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.