| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0891
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0041 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0995
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0337 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-089 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-099 |
| filingDate |
2000-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a6560c0d1d8b60bb7d6ea0220503c32 |
| publicationDate |
2002-02-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2002050960-A |
| titleOfInvention |
Digital phase control method, digital phase control circuit, and delay locked loop |
| abstract |
(57) Abstract: A digital phase in which a predetermined number of clock signals having the same frequency but different phases can be phase-shifted with high precision and high resolution as a whole while maintaining the phase interval at a predetermined interval. A control method and a digital phase control circuit are provided. One of the 14-phase first multi-phase clocks d1 to d7 and d1B to d7B having a fixed phase, and the 16-phase second multi-phase clocks e1 to e8, e1B to e1B. The phase of the second multi-phase clock is shifted by synchronizing the phase of one of the e8B clocks and switching the combination of clock signals to be phase-synchronized. Further, a circuit is used in which buffers constituting a delay line for generating the second multi-phase clock are connected in a ring. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009504064-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007097140-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8629699-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100483825-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7010074-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7350789-B2 |
| priorityDate |
2000-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |