http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002025273-A

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filingDate 2000-07-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_755fecf7688a0471a2cfd4427860945d
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publicationDate 2002-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2002025273-A
titleOfInvention Memory block and semiconductor memory device using the memory block
abstract (57) [Problem] To provide a semiconductor memory device capable of increasing a memory capacity without deteriorating an operation speed and suitable for being mixed with logic. SOLUTION: It is arranged corresponding to a memory cell array, A memory block operable independently having a data input / output circuit arranged in the order of data transfer and a control circuit arranged in the order of the critical path from the input buffer to the row decoder; A control circuit having a function of branching a signal and an external address signal in a memory block and controlling the operation of each memory block;
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Incoming Links

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Total number of triples: 23.