http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002009163-A

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filingDate 2001-04-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f7379fbc946a36fff1b66f49768b7c39
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publicationDate 2002-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2002009163-A
titleOfInvention Method of manufacturing laminated double polysilicon / MOS capacitor using SiGe integration mechanism
abstract (57) Provided is a stacked double polysilicon / MOS capacitor useful as a component of a BiCMOS device including a semiconductor substrate having a first conductivity type region formed on a surface thereof. A gate oxide overlapping a first conductivity type region is formed on a semiconductor substrate. A first polysilicon layer doped with an N-type dopant or a P-type dopant is formed at least on the gate oxide layer. A dielectric layer is formed on the first polysilicon layer. A second polysilicon layer doped with the same or different dopant as the first polysilicon layer is formed on the dielectric layer.
priorityDate 2000-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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