| abstract |
(57) [Summary] A structure in which a block of a random access memory or a RAM is integrated with a logic block that can be reconfigured with an FPGA. Routing lines that access the reconfigurable logic block also access the address, data and control lines of the RAM block. Thus, the logic blocks of the FPGA can use these routing lines to access portions of the RAM. In one embodiment, dedicated address and data lines access the RAM blocks of the present invention and are connectable to routing lines of the interconnect structure. These lines allow the RAM block and the array of RAM blocks to be formed to be long, wide, or between, and that the logic blocks conveniently access the RAM blocks on remote portions of the chip. Will be able to Access to the RAM block is efficient in any RAM configuration. The bi-directional buffer or pass device divides the address and data lines of each RAM block, so that a selectable number of RAM blocks can operate together as RAM. In another embodiment, the dedicated data lines can be programmably connected in an interleaved fashion so that the RAM blocks can be connected over long distances without collision between the RAM blocks. |