http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2001289909-A

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filingDate 2000-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2cf55acfe6aab743f5ef33c08756d0b0
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publicationDate 2001-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2001289909-A
titleOfInvention Failure analysis method and failure analysis device for semiconductor integrated circuit
abstract (57) [Problem] To efficiently estimate an internal fault location such as a delay fault or a disconnection fault without processing an IC element. SOLUTION: A series of two or more test patterns is integrated into an IC. To measure the transient power supply current of the IC at that time, determine whether or not the transient power supply current indicates an abnormality, and perform a logic simulation when the test pattern sequence indicating the abnormality is input to the IC. A logic value sequence generated in a signal line in the IC is calculated, and using the logic value sequence, a location where a transient current abnormality can be detected is generated as a failure location list according to the test pattern sequence. A common point in the failure point list for the pattern sequence is estimated as a failure point.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4559321-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-5522310-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2012124118-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2007046961-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012524392-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102854429-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006275700-A
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Total number of triples: 28.