| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0891 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0816 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-089 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06 |
| filingDate |
2000-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6a67a63237edf0b68e225d25c189f75 |
| publicationDate |
2001-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2001285266-A |
| titleOfInvention |
Digital phase control circuit |
| abstract |
(57) Abstract: Provided is a power-saving and small-area high-resolution digital phase control circuit in which an increase in power consumption and an increase in an area occupied by a circuit are minimized. A delay buffer having a propagation delay time of 160 ps is provided. A clock signal is extracted from any one of the voltage control delay line VCDL1 connecting the G10, the voltage control delay line VCDL2 connecting the delay buffers H1 to H8 having a propagation delay time of 200 ps, and the voltage control delay line VCDL1. The digital phase control circuit 10 comprises a selection circuit S2 for outputting to the first stage of the line VCDL2 and a selection circuit S3 for taking out and outputting a clock signal from any stage of the voltage control delay line VCDL2. The VCDL1 and the second voltage control delay line VCDL2 are feedback-controlled by the delay lock loops DLL1 and DLL2, and the phase of the clock signal is controlled with a resolution of 40 ps between 160 ps and 200 ps. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7149145-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114884964-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100922709-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7835205-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005509350-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005516327-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2009152866-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7298192-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7924074-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7010074-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7116146-B2 |
| priorityDate |
2000-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |