http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2001210837-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
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filingDate 2000-12-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6637ad17607617df38d5ce84d796446
publicationDate 2001-08-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2001210837-A
titleOfInvention Semiconductor device and method of manufacturing the same
abstract (57) [Abstract] [Purpose] To provide a highly reliable gate film which is hardly affected by a charge-up phenomenon, a plasma damage or static electricity in a manufacturing process and a mounting process, and in actual use. Provided is a semiconductor device including a thin film transistor having the same. A polycrystalline silicon thin film P-channel MOS transistor is an N + type polycrystalline silicon film 5 forming a gate electrode. And a polycrystalline silicon film 8 forming a bulk layer formed thereon via a silicon dioxide film 6 forming a gate film, and a P + type polysilicon forming source / drain regions formed on both sides thereof. A through-hole 7 is provided in a region of the silicon dioxide film 6 other than the region where the N + -type polycrystalline silicon film 5 is formed. are formed by 8 the same layer formation and, the P + -type polycrystalline silicon film 10 constituting the wiring layer, the sul - e - P + -type diffusion layer formed on the P-type silicon substrate 1 via the Le 7 3 is connected.
priorityDate 2000-12-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 22.