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filingDate 2000-10-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8de0748653091fffedac78962313eec0
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publicationDate 2001-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2001189321-A
titleOfInvention Lateral heterobipolar transistor and manufacturing method thereof
abstract Abstract: PROBLEM TO BE SOLVED: To provide a hetero bipolar transistor having a small parasitic capacitance and a small parasitic resistance and capable of lowering the resistance of an internal base layer, and a method of manufacturing the same. A so-called SOI structure in which a Si substrate, a BOX layer, and a semiconductor layer are stacked. The semiconductor layer 152 includes a collector 101 made of silicon and a SiGeC / Si layer 102 and emitter 1 made of n-type polysilicon 03 and an external base layer 104. Internal base layer 102a is composed of Si 1-x Ge x C y layer. Utilizing the heterojunction, it possible to reduce the resistance of the internal base layer, and it is possible to suppress the diffusion of the impurity in the intrinsic base layer formed of Si 1-x Ge x C y layer which is formed by epitaxial growth.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7119382-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013048274-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010129610-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2008114466-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013065626-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4714889-B2
priorityDate 1999-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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