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filingDate 2000-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2001-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2001156294-A
titleOfInvention Power MOS device and manufacturing method thereof
abstract (57) [Summary] [Problem] Power M for reducing capacitance between electrodes Provide an OS device. A power MOS device uses (1) a gate oxide having a thickness of at least 2 micrometers or more; (2) uses a stepped gate oxide; and (3) uses polysilicon from an area overlapping a drain. Etching, leaving two small polysilicon regions substantially above the channel, leaving no polysilicon region in the area above the drain; (4) etching a small section above the channel region to form three polysilicon regions. The gate-drain capacitance C GD is reduced by leaving an area made of silicon, two of which form a gate on the channel and a third in the area overlapping the drain.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2004006598-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2017228761-A
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