| abstract |
(57) [Summary] A plurality of chips ic1a, ic2a, ic3a Are integrated in the stacked device 41, and the boundary scan test can be executed with a small number of pins and only once. SOLUTION: Each chip ic1a to ic3a is equipped with a register such as a BSR in addition to the core logic, and a TAPC for controlling the register is a first-stage chip i. It is provided only in c1a, and the test command / data output and input signal lines TDO and TDI of the boundary scan test are connected in a loop through a wire WOI connecting between chips. Other signal lines TCK, TMS, TRST indicates that the chip ic1a has its output signal line T Distribute from AP0 to TAP4. As a result, the test can be executed with a small number of pins and once, The man-hour and area of the chips ic2a and ic3a without the TAPC can be reduced. |