| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1069
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1057
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-106
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-409
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 |
| filingDate |
1999-10-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3116ca349c5f7c36a17c5483c6d1758f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_feba6d9a7c073ca382cd5b12d762202b |
| publicationDate |
2001-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2001110185-A |
| titleOfInvention |
Clock synchronous semiconductor memory device |
| abstract |
[PROBLEMS] To provide a clock synchronous semiconductor memory device capable of shortening a clock access time. An output data control circuit (O) transfers a complementary data signal read from a memory array to an external data output node (Q) according to an output clock signal (CLK2). DC), a clocked gate circuit (12) for transferring a complementary data signal in synchronization with the output clock signal; An output data latch circuit (13) for latching an output signal of clocked gate circuit 12 is operated at a voltage level equal to or higher than the internal power supply voltage. The amplitude expansion process is performed and applied to the clocked gate circuit. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2013524318-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2002298582-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8891318-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012119849-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8856577-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008071474-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012105126-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9041436-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7719052-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8576634-B2 |
| priorityDate |
1999-10-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |