| abstract |
(57) [Summary] [PROBLEMS] To suppress poor alignment of liquid crystal. SOLUTION: A first flattening layer 10 is provided on a thin film transistor 2, a gate wiring 4 and a source wiring 7, and The first pixel electrode 12 is provided on the flattening layer 10 of the first embodiment, and the second flattening layer 11 is provided on the contact connecting the drain region and the first pixel electrode 12. The second pixel electrode 13 is provided on the second planarization layer 11. |