| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_04d2380bb7d1a032a47b7037a8346b3c |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8249
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-763
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0635 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8248
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-763
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01C17-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01C13-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8249 |
| filingDate |
2000-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6aa8a88a796fb328cd3ddfbb5417611c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e1063c52cfac144e695f7a7ecab21492
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2429bf1bf9d6b9650eb749a982232cf0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f6f418b469e6f1765002a0b27541196a |
| publicationDate |
2001-03-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2001060668-A |
| titleOfInvention |
Improved BiCMOS process with resistor with low temperature coefficient of resistance (TCRL) |
| abstract |
(57) [Summary] (With correction) [PROBLEMS] To provide a method of manufacturing a thin film resistor having a relatively small temperature coefficient of resistance. SOLUTION: A resistor (TCR) having a small temperature coefficient of resistance. L) is typically formed on an insulating film such as silicon oxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of one or more dopants. With implanted resistors, a shorter annealing step is utilized than with typical prior art implanted resistors, which results in the intended unannealed damage to the resistor. With the designed damage, High resistance is given to TCRL without increasing the temperature coefficient. The resistor fabrication method is used in conjunction with a separate spacer oxide deposition to provide buried layers with different diffusion coefficients, introduce dual oil field trench sidewalls to bounce off as a polishing stopper, and to precisely control emitter-base dimensions. Provide structure and integrate bipolar and CMOS devices with negligible compromises of any type of feature. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100486112-B1 |
| priorityDate |
1999-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |