| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f481982f9992cbb527a6d31589832958 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-033 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-91
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-55 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 |
| filingDate |
2000-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21e2c078800aca684b6425723a2ffa19
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93576a0e327c94e717af2fe9390576e7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_74a5332ed1987232588d754b3a231ee1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b9d7617ac6d2b94bba44aa1ecc2c6239 |
| publicationDate |
2000-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2000332221-A |
| titleOfInvention |
Integrated circuit and method |
| abstract |
PROBLEM TO BE SOLVED: To provide a capacitor structure which is compatible with CMP used in a multilayer structure which is compatible with standard / low-temperature processing technology and improves the density of capacitance. SOLUTION: The capacitor structure of the present invention is formed in an opening of a dielectric layer of an integrated circuit. The lower electrode layer extends over at least a portion of the side surface of the opening, but does not extend to the upper surface of the dielectric layer. A layer of dielectric material is disposed on the lower electrode and on an upper surface of the integrated circuit dielectric layer. Finally, an upper electrode layer is formed over the dielectric material layer. There is no overlap between the upper and lower electrode layers, thus avoiding short circuit problems that may occur during the planarization process. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100456577-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100414873-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2006128320-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7029983-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7763922-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-4646595-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005294841-A |
| priorityDate |
1999-05-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |