http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2000215664-A

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
filingDate 1999-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3e10903008483b9a747df7a3ce99427e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_196963efe5d003e79d87d61bd6f0209b
publicationDate 2000-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2000215664-A
titleOfInvention Semiconductor integrated circuit device and semiconductor storage device
abstract (57) Abstract: Provided is a semiconductor memory device capable of generating and erasing each internal clock signal with a constant relation without changing the generation timing. A latch circuit latches a main power down signal CKEMZ in response to an internal clock signal CLKSZ from a first clock signal input buffer. The latched internal power-down signal CKECZ is held by the first enable signal generation circuit 15 as the first enable signal ENZ1 in response to the internal clock signal CLKSZ. And the first The enable signal ENZ1 is output to the first gate 17 and Controls the internal clock signal CLKM1. Also, the first enable signal held by the first enable signal generation circuit 15 The ENZ1 is held as a second enable signal ENZ2 in response to the internal clock signal CLKSZ by the second enable signal generation circuit 16, and the first and second clock signal input buffers 1 1 and 12 are output.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100826649-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100856062-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2008091000-A
priorityDate 1998-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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